1. Technical Field
Various embodiments of the present invention relate to a semiconductor memory apparatus. In particular, certain embodiments relate to a semiconductor memory apparatus including a page buffer circuit.
2. Related Art
A typical semiconductor memory apparatus, such as a NAND flash memory, includes a memory cell array as a storage region for storing information and a page buffer circuit for storing data in the memory cell array or reading data from the memory cell array.
In addition, a semiconductor memory apparatus, such as a NAND flash memory, is classified into a Single Level Cell (SLC) scheme, a Multi Level Cell (MLC) scheme, and a Triple Level Cell (TLC) scheme, depending on the number of data bits that can be stored in a single memory cell.
A page buffer circuit often includes latch circuits for temporarily storing data, and the number of the required latch circuits varies depending on the SLC, MLC, and TLC schemes. For example, the MLC scheme requires one cache latch, one main latch, and two sub latches. The TLC scheme requires one cache latch, one main latch, and three sub latches.
The latch circuits included in the page buffer circuit may be configured with a typical latch and a dynamic latch. A typical latch has excellent data retention ability and driving ability but occupies a large area. Accordingly, in order to reduce the total size of the page buffer circuit, the latch circuit is often configured with a dynamic latch which is advantageous in terms of area.
FIG. 1 is a schematic diagram of a typical page buffer circuit using a dynamic latch as a sub latch.
The page buffer circuit may include a main latch unit 10 and a sub latch unit 20.
The main latch unit 10 usually exchanges data with a cache latch circuit (not shown) and a memory cell array (not shown). Since the cache latch circuit (not shown) and the memory cell array (not shown) are not essential for describing the background of the present invention, a description thereof will be omitted.
The main latch unit 10 may include a latch circuit having a main latch value. The main latch unit 10 is configured with a typical latch circuit in order to have large driving ability enough to exchange data with the memory cell array. The dynamic latch has an advantage over the typical latch circuit due to its narrow footage, but it is less suited to be used as the main latch unit 10 because driving ability of a dynamic latch is lower than that of a typical latch circuit. The main latch value of the main latch unit 10 may vary depending on data communicating with the cell array, data communicating with the cache latch circuit, and a sub latch output signal SLO.
The sub latch unit 20 stores the main latch value at a storage node ns as a sub latch value according to a storage enable signal F1SET. In addition, the sub latch unit 20 outputs a storage latch value as the sub latch output signal SLO according to an output enable signal F1TRAN.
The sub latch unit 20 latches temporary data received from the main latch unit 10, and recovers the temporary data to the main latch unit 10 through a sub latch signal DLS.
Therefore, when the sub latch unit 20 receives the temporary data from the main latch unit 10, the sub latch unit 20 should be able to retain the temporary data while the main latch unit 10 exchanges data with the cell array or the cache latch.
However, in FIG. 1, when a connection node nt is at a low level and the storage node ns is at a high level, the voltage level of the storage node ns, which is the storage latch value, is lowered due to a leakage current of a transistor 101. That is, an error may occur in the storage latch value by the leakage current.
Accordingly, a method of increasing static capacitance appearing at the storage node ns by coupling a capacitor transistor 104 to the storage node ns can be used, but such a capacitor transistor 104 may occupy a relatively large area.
In addition, a refresh operation is periodically performed in order to maintain the voltage level of the storage node ns. The refresh operation is an operation in which the storage latch value is transmitted to the main latch unit 10 as the sub latch output signal SLO while the main latch unit 10 does not communicate with the cache latch or the memory cell array, and the main latch unit 10 receives the sub latch output signal SLO as the main latch value and again transmits the received sub latch output signal SLO to the storage node ns of the sub latch unit 20 as the storage latch value.
However, since such a refresh operation uses the main latch unit 10, the operating speed of a flash memory apparatus is lowered.
As mentioned above, in the case of the MLC scheme, the page buffer circuit includes two sub latches and, in the case of the TLC scheme, the page buffer circuit includes three sub latches.
Since the operating speed of the page buffer circuit is usually lowered by the refresh operation, dynamic latches are not used as the two sub latches. That is, the dynamic latch is used as one or none of the sub latches, and the typical latch circuit is used as the other sub latch. The typical latch circuit is disadvantageous to the integration of the semiconductor apparatus because it occupies a larger area as compared to the dynamic latch circuit.